M xywrun.c → xywrun.c

@@ -209,14 +209,14 @@ // clang-format off
 
 //// Operations that support stack and all registers
 #define OPC_SR2(opc, body) { \
-    case opc: { const xyw_byte w = 0, rx=0, ry=0, a = us_pop(), b = us_pop(); body; } break; \
-    case XYW_MODE_X|opc: { const xyw_byte w = 0, a = *x, b = us_pop(), rx=1, ry=0; body; } break; \
-    case XYW_MODE_Y|opc: { const xyw_byte w = 0, a = *y, b = us_pop(), rx=0, ry=1; body; } break; \
-    case XYW_MODE_X|XYW_MODE_Y|opc: { const xyw_byte w = 0, a = *x, b = *y, rx=1, ry=1; body; } break; \
-    case XYW_MODE_W|opc: { const xyw_byte w = 1, rx=0, ry=0; xyw_word a = us_popw(); xyw_word b = us_popw(); body; } break; \
-    case XYW_MODE_X|XYW_MODE_W|opc: { const xyw_byte w = 1, rx=1, ry=0; xyw_word a = *xw; xyw_word b = us_popw(); body; } break; \
-    case XYW_MODE_Y|XYW_MODE_W|opc: { const xyw_byte w = 1, rx=0, ry=1; xyw_word a = *yw; xyw_word b = us_popw(); body; } break; \
-    case XYW_MODE_X|XYW_MODE_Y|XYW_MODE_W|opc: { const xyw_byte w = 1, rx=1, ry=1; xyw_word a = *xw; xyw_word b = *yw; body; } break; \
+    case opc: { const int w = 0, rx=0, ry=0; xyw_byte a = us_pop(), b = us_pop(); body; } break; \
+    case XYW_MODE_X|opc: { const int w = 0, rx=1, ry=0; xyw_byte a = *x, b = us_pop(); body; } break; \
+    case XYW_MODE_Y|opc: { const int w = 0, rx=0, ry=1; xyw_byte a = *y, b = us_pop(); body; } break; \
+    case XYW_MODE_X|XYW_MODE_Y|opc: { const int w = 0, rx=1, ry=1; xyw_byte a = *x, b = *y; body; } break; \
+    case XYW_MODE_W|opc: { const int w = 1, rx=0, ry=0; xyw_word a = us_popw(); xyw_word b = us_popw(); body; } break; \
+    case XYW_MODE_X|XYW_MODE_W|opc: { const int w = 1, rx=1, ry=0; xyw_word a = *xw; xyw_word b = us_popw(); body; } break; \
+    case XYW_MODE_Y|XYW_MODE_W|opc: { const int w = 1, rx=0, ry=1; xyw_word a = *yw; xyw_word b = us_popw(); body; } break; \
+    case XYW_MODE_X|XYW_MODE_Y|XYW_MODE_W|opc: { const int w = 1, rx=1, ry=1; xyw_word a = *xw; xyw_word b = *yw; body; } break; \
 }
 
 //// Operations that support stack and one register